How to Design a TEC Cooling System | TEC Module, Heat Sink, Sensor & Mounting Stack Guide

Time : Jun 29 2026Source :Analog Technologies, Inc. Author : Fang Click :

White Paper AWP-TECC-03 · Rev 2.9 · June 2026 · Analog Technologies, Inc.

Download the full white paper (PDF):  AWP-TECC-03 — How to Design a TEC Cooling System

How do I design a TEC cooling system?

Designing a TEC cooling system is a six-step process: characterize the cold-side thermal load, define the worst-case ambient envelope, select a TEC module from its datasheet performance curves at the actual operating point, size the heat sink for the resulting hot-side heat, choose the sensor placement and mounting, and validate the assembled stack against a worst-case test envelope before production. The TEC controller is selected separately per companion paper AWP-TECC-02.

Four components must be sized together against the application's thermal load, ambient envelope, and target setpoint: the TEC module (heat-pumping capacity at worst-case ΔT), the heat sink (Q_hot rejection at worst-case ambient), the temperature sensor (placement that determines what the loop can resolve), and the mechanical stack (TIM, compression, orientation, sealing).

Key equations:
Q_hot = Q_c + P_electrical  ·  P_electrical = V_TEC × I_TEC
ΔT_TEC = T_hot − T_cold,setpoint  ·  R_θSA ≤ (T_hot,max − T_ambient,max) / Q_hot

Starting design path by application

Application Cold-side load ΔT TEC module direction Heat-sink direction
Miniaturized photonic sensor (Raman, gas analyzer)≤ 1 W≤ 20 °CCompact single-stagePassive or small forced-air
Laser-diode wavelength stabilization0.5–5 W15–35 °CSingle-stage matched to packageForced-air, controlled airflow
Mid-power precision (OCXO, photodetector, ADC)1–10 W15–40 °CSingle-stage, COP-oversizedForced-air with margin
PCR / instrumentation thermal block10–30 W40–90 °CCycle-life-rated single-stageForced-air, cycle margin
Outdoor kiosk / enclosure cooling20–60 WWindow-modeEnclosure-class single-stageForced-air, dust margin

Six-step TEC cooling system design methodology

  1. Determine the cold-side thermal load. Q_load = Q_active + Q_passive at worst-case operating point. Active loads include laser diodes, GPUs, photodetectors. Passive loads are heat flowing into the cold object via convection, conduction, and radiation.
  2. Define temperature requirements. Setpoint, worst-case ambient at heat sink, and required ΔT across the TEC.
  3. Select the TEC module. Read I_TEC and V_TEC from datasheet performance curves at the operating point. Use 60–70% of I_max for general OEM (practical sizing), or 25–30% for battery / long-life applications (high-COP).
  4. Match controller to TEC. Controller I_max ≥ 1.5–2× I_TEC; V_max + supply rail must cover V_TEC + V_dropout at worst-case hot ambient. See companion paper AWP-TECC-02.
  5. Choose design priority. Minimize input power, minimize size/cost, maximize ΔT, or autonomous enclosure cooling — each maps to a different ATI family.
  6. Size the heat sink. R_θSA ≤ (T_hot,max − T_ambient,max) / Q_hot. Apply 1.5–2× margin for lab/production, 2–3× for industrial OEM, 3–5× for outdoor or dusty environments.
Common TEC sizing mistake: combining Q_max and ΔT_max
Q_max (published at ΔT = 0) and ΔT_max (published at Q_c = 0) are end-points of the TEC's performance curve and cannot both be achieved simultaneously. Read Q_c at the actual operating point (I_TEC, ΔT_TEC, T_hot) from the datasheet performance curves and verify Q_c ≥ Q_load there.

Sensor placement and sub-10 mK design rules

Controller datasheet stability is measured at the sensor under defined laboratory conditions. Stability at the controlled object depends on the full thermal stack. For sub-10 mK (<0.01 °C)-class targets:

  • Controller placement — well-ventilated; body-temperature drift translates to setpoint drift.
  • Topology — prefer hybrid or well-filtered switching over pure-linear.
  • Heat sink — constant fan speed; no variable airflow on load or sink; enclose to exclude external drafts.
  • Sensor — small NTC bead, thin leads, within 5 mm of the load, in a step (counter-bored) hole, not a straight through-hole.
  • V_PS and TMS pin — manage low-frequency drift and audio-band noise; TMS noise converts directly to temperature command error scaled by V/°C.

TEC mounting and assembly

Critical orientation rule — For standard ATI TEC modules, the label and printing are on the COLD side. The label side must face UP toward the load; the wire side faces DOWN toward the heat sink. Reversing this drives heat the wrong way and heats the load.

A poorly assembled stack can lose 20–40% of cooling capacity to parasitic resistance at TIM interfaces. Apply thin uniform TIM (target 25–100 µm) on both ceramic faces. Lap mating surfaces flat to ±0.025 mm (TIR ≤ 0.076 mm). Use four screws with spring washers for uniform compression (typical target 1.0–2.0 MPa over ceramic-face area — verify against the specific module's datasheet).

TIM thickness and per-interface thermal resistance

TIM thickness R_TIM per interface Temperature penalty at 12 W
50 µm (ideal)0.05 °C/W0.6 °C
100 µm (acceptable)0.10 °C/W1.2 °C
200 µm (too much)0.20 °C/W2.4 °C
500 µm (excessive)0.50 °C/W6.0 °C

Recommended ATI controllers by application

If You Need… Load Range Family Group Example Part Number
Smallest footprint≤ 1 WTEC14M (14 × 14 mm SMT)TEC14M5V3R5AS
General OEM prototyping1–3 WTECA1 (DIP)TECA1-5V-5V-DAH
Lower-mid-power 5 V2–4 WTEC5V (hybrid, 4 A)TEC5V4A-DAH (or -LD)
Mid-power 5 V4–10 WTEC5V (hybrid, 6 A)TEC5V6A-DAH (or -LD)
High current / high ΔT10–50 WHigh-current seriesTEC18V15A, TEC24V10A, TEC24V15A
Autonomous enclosure cooling20–60 WATFC (window mode + fan PWM)ATFC106D (12 V)

Why ATI for OEM TEC cooling systems

ATI's hybrid topology (U.S. Patent 6,486,643 B2) delivers high efficiency together with low output ripple in a single module — substantially reducing the external LC filtering that pure-PWM controllers require, while avoiding the controller self-heating penalty of pure-linear designs. ATI supplies matched TEC controllers, TEC modules, precision thermistors, and evaluation boards from a single source, simplifying compatibility checks across the controller-sensor-TEC operating envelope. US-based applications engineering reviews qualified OEM project specifications and recommends a starting controller family, precision grade, and evaluation board.

Regulated-Use Caveat — ATI TEC controllers, modules, and thermistors are commercial-grade components. System-level qualification for medical (FDA, IEC 60601, ISO 13485, IVDR), automotive (AEC-Q, ISO 26262), aerospace (RTCA DO-160), and other regulated end products remains the OEM's responsibility.
Next step — order the matched evaluation board

The fastest path from this guide to a working prototype is to validate compensation tuning on the matched eval board against your actual thermal load before committing to a PCB layout:
  • ≤ 1 W miniature SMT → TEC14M5V3R5AS with TEC14MEV1.0
  • 1–3 W laser-diode / photonic → TECA1-5V-5V-DAH with TECEV104
  • 4–10 W mid-power 5 V → TEC5V6A-DAH (or -LD) with TECEV104
  • 10–50 W high-current → TEC18V15A / TEC24V10A / TEC24V15A on shared TEC24V15AEV2.2
  • 20–60 W enclosure cooling → ATFC106D (self-contained)

Order at shop.analogtechnologies.com. For applications outside these envelopes, contact ATI applications engineering.

Download the full white paper (PDF):  AWP-TECC-03 — How to Design a TEC Cooling System (Rev 2.9, June 2026, PDF)
Full 39-page guide: complete six-step methodology, sub-10 mK design rules, mounting assembly procedure, five worked application examples (laser-diode, PCR, kiosk, photonic sensor, LIDAR), validation envelope, and selection-support form.

Contact ATI

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